1. Field of the Invention
The invention relates in general to an image processing module, and more particularly to an image processing module with less line buffers.
2. Description of the Related Art
If resolution of the image signal is different from the resolution of the display, the resolution must be adjusted in the course of image processing. That is, a scaler is used to adjust the image signal with different resolution to the resolution of the display. Referring to FIG. 1, a block diagram of a conventional image processing system is shown. Image processing system 100 includes a scaler 110 and a timing controller 120. The scaler 110 receives and registers the original image signal Si in the line buffer 111, the original image signal Si is scaled and the resolution of the original image signal Si is adjusted, and then an image signal S1 is outputted. The timing controller 120 receives the image signal S1 and outputs a display signal S2 according to the image signal S1 to drive the display panel 130.
As the resolution of video image increases, data volume and transmission speed also increase. However, a few problems, such as electromagnetic interfering, (EMI) for instance, also arise at the same time. Therefore, another image processing system structure in response to high resolution image processing is provided. Referring to FIG. 2, a block diagram of a conventional image processing system capable of processing high resolution image is shown. Image processing system 200 includes a scaler 110 and a timing controller 220. The scaler 110 includes a line buffer 111. The scaler 110 receives and registers the original image signal Si in the line buffer 111, the original image signal Si is scaled and the resolution of the original image signal Si is adjusted, and then an image signal S1 is outputted. The timing controller 220 includes a line buffer 221. The timing controller 220 receives and registers the image signal S1 in the line buffer 221, the timing in the data of the image signal S1 is changed, and then a front-display signal Sf and a back-display signal Sb are outputted to drive the display panel 230.
The main difference between the image processing system of FIG. 2 and that of FIG. 1 lies in the timing of the data of the display signal transmitted to the display panel. In FIG. 1, the timing controller 120 transmits the pixel data of the same horizontal line in the display signal S2 from left to right to the display panel 130. In FIG. 2, the timing controller 220 divides the frame of the display into a front frame and a back frame. That is, each horizontal line is divided into a front-horizontal line and a back-horizontal line. The timing controller 220 transmits the image data of the front-horizontal line and the back-horizontal line to the display panel 230 at the same time. Referring to FIG. 3A, a pixel diagram of the display panel 130 is shown. The display panel 130 has a horizontal line L1. The horizontal line L1 has a pixel 1, pixel 2, pixel 3, and pixel 4 etc. The timing controller 120, following the sequence of the pixel 1, the pixel 2, the pixel 3 and the pixel 4, transmits the corresponding display signals S2 to the display panel 130 sequentially. Referring to FIG. 3B, a diagram of dividing the display panel 230 into a front frame and a back frame is shown. The display panel 230 has a horizontal line L2. The horizontal line L2 is divided into a front-horizontal line L2f and a back-horizontal line L2b. The front-horizontal line L2f includes a pixel f1, a pixel f2 and a pixel f3. The back-horizontal line L2b includes a pixel b1, a pixel b2 and a pixel b3. The timing controller 120, following the sequence of the pixel f1, the pixel f2 and the pixel f3, transmits the corresponding front-display signals Sf to the display panel 230 sequentially, while the timing controller 120, following the sequence of the pixel b1, the pixel b2 and the pixel b3, transmits the corresponding back-display signals Sb to the display panel 230 sequentially.
In order to simultaneously output the front-display signal Sf and the back-display signal Sb, the timing controller 220 needs a line buffer 221 in which the data are registered. However, in order to meet the standard of high resolution, both the scaler 210 and the timing controller 220 are equipped with a line buffer, which is redundant and uneconomical.